Author Topic: TPL5110 Timer: Avoiding the forced 50ms power interrupt if no DONE signal  (Read 195 times)


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Reading the TPL5110 datasheet, it says that power will be interrupted for the last 50ms of the cycle if no DONE signal is received.  I am trying to do low power listen about once per second and if I hear a signal then I am going to take an action for longer than one second.  Thus, I need a way to delay or avoid or otherwise get around that 50ms power interruption.  Any ideas? 

It is similar to this Texas Instruments thread, but I am not sure how what an RC circuit is.  It seems like its a capacitor that provides power to bridge that 50ms gap, but wouldn't that mean that power is still delivered to the system for 50ms even when the DONE signal is sent?