LowPowerLab Forum
Hardware support => Low Power Techniques => Topic started by: arf on July 28, 2021, 11:29:41 PM
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Reading the TPL5110 datasheet (https://www.ti.com/product/TPL5110), it says that power will be interrupted for the last 50ms of the cycle if no DONE signal is received. I am trying to do low power listen about once per second and if I hear a signal then I am going to take an action for longer than one second. Thus, I need a way to delay or avoid or otherwise get around that 50ms power interruption. Any ideas?
It is similar to this Texas Instruments thread (https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/921169/tpl5110-q1-how-to-avoid-forced-drive-reset), but I am not sure how what an RC circuit is. It seems like its a capacitor that provides power to bridge that 50ms gap, but wouldn't that mean that power is still delivered to the system for 50ms even when the DONE signal is sent?
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This is a late reply, but if it's not solved or if someone else facing same issue, you could consider to use TPL5010 instead of the TPL5110. The TPL5010 is a watchdog who won't cut off your power, it will only send a wakeup signal to wake up your
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Thanks Buzz. The issue is that the rest of the system is not made for low power sleeping, so I was trying to hard cut the power. Another problem I ran into was that the boot time for the rest of the system (M0) was quite long and that messed up my duty cycle ratios.