Author Topic: Send timing jitter and latency regression in master branch  (Read 171 times)


  • Newbie
  • *
  • Posts: 38
Send timing jitter and latency regression in master branch
« on: August 28, 2019, 04:46:09 PM »
Hi Felix,
   I have an application that requires very tight timing to synchronize a periodic signal wirelessly, and I wrote an algorithm that self-measures the time to send/receive packets is able to synchronize 2 Moteino M0s down to <10 uS with the 1.3.0 library.
  However, with the new library in the master branch, there is an additional ~3.5ms of latency, and the jitter has increased to about 25 uS.  I tracked down the changes that caused this to the sendFrame function:

Code: [Select]
  setMode(RF69_MODE_STANDBY); // turn off receiver to prevent reception while filling fifo
  while ((readReg(REG_IRQFLAGS1) & RF_IRQFLAGS1_MODEREADY) == 0x00); // wait for ModeReady
  //writeReg(REG_DIOMAPPING1, RF_DIOMAPPING1_DIO0_00); // DIO0 is "Packet Sent"
  //while (digitalRead(_interruptPin) == 0 && millis() - txStart < RF69_TX_LIMIT_MS); // wait for DIO0 to turn HIGH signalling transmission finish
  while ((readReg(REG_IRQFLAGS2) & RF_IRQFLAGS2_PACKETSENT) == 0x00); // wait for PacketSent

I was wondering, what were these changes supposed to do?

I fixed the timing in my circuit by re-enabling the DIO0 write at the top; I was using the interrupt to trigger a timer for self-measuring. 
« Last Edit: August 29, 2019, 09:41:56 PM by mah115 »


  • Administrator
  • Hero Member
  • *****
  • Posts: 6266
  • Country: us
    • LowPowerLab
Re: Send timing jitter and latency regression in master branch
« Reply #1 on: August 30, 2019, 10:22:02 AM »
If you look at this commit, it went from doing pin polling to register polling, without the interrupt being set to "Packet Sent" because it was not being used.
I made these changes after some scope timing measurements, and this should be faster code.
You can always re-enable the Packet Sent interrupt as you mentioned, if you need it.