To my mind, kulozik is right. On my schematics with a battery charger like this (MCP73831 or MCP73123) I put the Pmos symetrically : When charging, the 5V from usb lock the Pmos gate and avoid the battery (and the charger) to supply some power through the Pmos, and since the 5V even with drop through the diode is higher than the battery voltage, the diode of the Pmos lock the current to go into the battery.
Without 5V, the battery current can go through the diode of the Pmos, and as the gate come to 0V, the Pmos is unlocked.
I use some Pmos wich start to conduct at about 1V like DMP2005UFG, DMP2005UFG, SiA427DJ and equivalents (full opened at 4.5V, but very low Rds at 2.5V), we just have to check the leakage current which could be as high as 10µA on some very low Vgs Pmos.
With your schematics, The ~5V from VUSB_OR_VBAT can charge the battery if to the 2 drops from the shotky and the diode inside the Pmos are lower to 0.8V
I can add than I have no weird stuff happening when there's no battery plugged
Note from microchip :
http://ww1.microchip.com/downloads/en/appnotes/01149c.pdf on page 2