Just an unvetted idea (and this may be going overboard), but if one mapped DIO0 to ModeReady after the RFM69 enters into Stdby mode, as it of course does periodically while in Listen Mode, then DIO0 should go low the instant Stdby mode is left in order to transition into PllLock mode. So, if one used that as the trigger to wake the atmega328p (which takes ~4uSec), which then immediately reset the RFM69, then perhaps one could avoid expending the energy that would otherwise be consumed in the PllLock phase plus the minimum 64uSec of Rx phase.
[Edit: It would, of course, require access to the RST pin on the RFM69, but that could be bodged on.]