The way to achieve voltage conversion with very high efficiency at ultra low currents is to only run the converter intermittently and smartly disconnect it in between.
I took another pass at this, and it looks as though the savings would accrue from avoiding the quiescent current, which on an LTC3531-3.3 would be 7uA. Looks as though the WAKE pin on a TPL5010 could simply be wired to the !STDN pin on a LTC3531-3.3 (
http://cds.linear.com/docs/en/datasheet/3531fb.pdf), used to charge the cap, and
voilĂ . The WAKE pulse lasts 20ms, and the turn-on time for the LTC3531-3.3 takes less than 2ms, so it can buck/boost a solid 18ms per cycle with no need to wake the atmega. So, doing the tally for the "typical" case between wake-ups:
sleeping atmega: 100nA
sleeping RFM69: 100nA
shutdown LTC3531-3.3: 100nA
TPL5010: 35nA
Total: 335nA
So, not as thrifty as your circuit between wake events. I don't know what the periodicity of the wake-cycle would be, but if I were to go this route, I'd probably use either an RTC or another TPL5010 to wake the atmega as infrequently as possible. So, that would bring the total to, say, 370nA.
If those numbers proved out, that would open whole new horizons. What's next after that?