Hey
I want to use the tpl5110 as an external watchdog which can
cycle power if the MCU freezes and is not able to send the done
signal within the set delay period.
However, right now when the MCU is running the done signal
is causing the tpl to switch off the MCU for the remainder of
the delay period and power it on subsequently.
How do I prevent this?
Rgds
Karan
You set a TPL timeout with the resistors.
When the timeout expires you get a quick power-off and power-on. That is equivalent to a reset, except power is cutoff for a brief time, see datasheet.
If you assert DONE sooner (the normal case) then power-off happens at that time, and power-on resumes at the start of the next cycle.
If your system needs to keep some device/timer ON all the time then this might not work, or you might need to keep power on separately to that device/timer.
Quote from: designDemon on October 02, 2018, 09:59:16 AM
I want to use the tpl5110 as an external watchdog which can
cycle power if the MCU freezes and is not able to send the done
signal within the set delay period.
The TPL5110 is a different function than the TPL5010 Watchdog timer.
Think of the TPL5110 as a super low power timer that keeps your main function turned completely OFF until a set time has elapsed. Once that time has elapsed, the TPL5110 will power up your main device, which does whatever it is supposed to do and then literally signals 'Done' to power itself off. Consequently the only time there is any measurable power drawn on your battery is the brief time your function is active.
It really can't be configured conveniently as a Watchdog. The TPL5010, however, is an excellent Watchdog, resetting your device if it doesn't keep signalling 'Done'.
I would also recommend the TPL5010 if you are REQUIRED to have your device always powered or only want the pure reset and not power cycle.
My previous statement about an MCU/timer is technically incorrect because normally a MCU even if only reset, would also reset any timers so there is no advantage in that case with the TPL5010.
BUT to me, practically, a pure reset and a power cycle "reset" are basically the same thing.
The 5010 watchdog is still on a timeout cycle. The difference is that it does not ever cut power off for power saving purposes, so it does not interfere with what the MCU is doing, it only issues a RESET to the MCU RST pin if timeout expires before a DONE signal (ie watchdog "clear/reset") is received.
I would call the TPL5110 a timer and a pseudo-watchdog. If your MCU cannot be powered down for power savings, then yes, the 5110 cannot be used as a watchdog.
You can use its ability to power your device off and back on, as a fake "reset".
Your device is supposed to signal DONE within the timeout period - this is the normal case where the device does not lock up and is able to finish the task long time before the timeout.
If the device becomes unresponsive and the timeout expires, then the TPL5110 will power cycle it ("reset" it). So inherently it's a sort of (improper) watchdog.
The atmega1284 has an internal watchdog,
but when we were testing it for its reliability, we noticed
that if we externally short the SDA pin when i2c is live,
the uC freezes and the internal watchdog stops
working and only an external reset solves this problem.
So we started looking for an external watchdog to pre-empt
this case in our production devices.
Recently, we also encountered a case where not even a reset
and only an external power cycle would "unfreeze" our micro-
controller.
(in both the above cases we are quite sure that it was not
a firmware level bug and the watchdog function was indeed
enabled and initialised)
So we were looking for an external watchdog solution that
could power cycle our device incase it froze in the production
environment and stumbled upon the tpl5110 and tpl5111, and
were happy to see that LPL had a breakout board for it.
Are you guys saying that the normal watchdog function where
the watchdog timer resets ( or power cycles in the case of 5110)
the uC if an "all OK" pulse is not received before there
is a timeout, is not achievable with the 5110? Because, currently
the done signal is not only reseting the timer (which is desirable)
but is also turning the uC off. Ideally it should have
kept the uC on, reset the timer, and only if the done signal was
not received, initiated a quick power cycle to reset the uC.
I'm evaluating the 5010, but it still doesn't solve the case where
a power cycle might be necessary.
Thanks for your replies
Karan
Quote from: designDemo
Are you guys saying that the normal watchdog function where
the watchdog timer resets ( or power cycles in the case of 5110)
the uC if an "all OK" pulse is not received before there
is a timeout, is not achievable with the 5110? Because, currently
the done signal is not only reseting the timer (which is desirable)
but is also turning the uC off.
As Felix and Tom said, the TPL5110 will powered your MCU only from a periodic start, until the"done" signal from the MCU, telling it has finished its job.
If you need a power off/power on cycle when the MCU is not responding, maybe you could use the TPL5010 but instead of driving the reset pin of your MCU, you could drive the gate of a mosfet to cut of the power suply of your MCU a short time ? I don't know if the pulse is long enough to completely shutdown your MCU
Quote from: Uncle Buzz on October 03, 2018, 10:08:07 AM
I don't know if the pulse is long enough to completely shutdown your MCU
I believe the reset pulse width is 350mS.
Quote from: designDemon on October 03, 2018, 04:56:16 AM
Are you guys saying that the normal watchdog function where
the watchdog timer resets ( or power cycles in the case of 5110)
the uC if an "all OK" pulse is not received before there
is a timeout, is not achievable with the 5110? Because, currently
the done signal is not only reseting the timer (which is desirable)
but is also turning the uC off. Ideally it should have
kept the uC on, reset the timer, and only if the done signal was
not received, initiated a quick power cycle to reset the uC.
The TPL5110 is really a very low power timer and it would take an 'unnatural' act to get it to operate as a watchdog. It's purpose is to power on a circuit for only a brief amount of time where 'Done' signals termination of that power cycle with a safety margin guaranteeing a power off if Done isn't signaled by the next interval.
Quote
I'm evaluating the 5010, but it still doesn't solve the case where
a power cycle might be necessary.
I would recommend the 5010 for your application. For your needs, as @Uncle Buzz suggested, I'd use the Reset pin on the 5010 to drive the gate of an N channel FET (rather than MCU reset), which, in turn, drives a P channel load switch.
On power application, the Reset pin will be low and ensure that Power is not applied to the rest of the circuit until the 5010 initializes, then, the load switch will be turned on (assuming a pullup on 5010's Reset pin) and your circuit will be turned on.
From that point on, the 5010 will generate Wake signals, which, in your case, maybe can be ignored. However, as your circuit loops normally, it should pulse Done at least once within every time interval (and once on startup). If this is missed, then Reset will be pulled low turning off power to your MCU circuit for about 350mS.
Tom
I would too use a 5010 and if you want to ensure it's back up after a freeze, use the FET method suggested above.
To rephrase ... the 5010 will issue a hard reset, but not cut power (well unless you do the little hack to drive a FET instead of the MCU's RST pin).
The 5110 will always cut power (when DONE is received, or at timeout expiration). Probably in a lot of cases cases that's not acceptable, and normally the MCU has to keep going. In that case use the 5010.
Thanks for this guys.
Quote from: TomWS on October 03, 2018, 10:50:44 AM
I would recommend the 5010 for your application. For your needs, as @Uncle Buzz suggested, I'd use the Reset pin on the 5010 to drive the gate of an N channel FET (rather than MCU reset), which, in turn, drives a P channel load switch.
I am quite the rookie here. I would be grateful if you recommend a FET and sketch a
rough schematic here. For the load switch can I use this -
https://www.diodes.com/assets/Datasheets/DMP2045U.pdf ?
It is the suggested replacement for the one that is used in the current 5110-breakout.
- Karan
Quote from: designDemon on October 04, 2018, 03:28:06 PM
I would be grateful if you recommend a FET and sketch a
rough schematic here.
For a quick sampling, here is a snip from one of my schematics.
The part is a two transistor device from Vishay, Si1869DH. A complete loadswitch.
VBAT (TPL5010 VCC) should be connected to pin 4 of the loadswitch. Pin 5 (N channel gate) is tied to TPL5010 Reset pin and also needs a pullup to VBAT (value is arbitrary 10K-200K range). And your MCU power is driven by pins 2 & 3 of Q1. They're connected internally, but I'd tie them together on the PCB as well.
UPDATE: Sorry, R27 in the schematic should be set to a high value resistor since it is normally always in conduction. 3-10Mohm is probably ok but check the datasheet for pin 6 leakage current so you can guarantee that the loadswitch will turn off properly.
Hey Thanks so much TOM
is this schematic OK?
I've connected the wakeup pin to the interrupt pin d10
and the done is a GPIO. The jumpers are just in case
I decide I don't wish to power cycle.
(https://ibb.co/guM4ie)
I've replaced the vishay mosfet with tps27081a (http://www.ti.com/lit/ds/symlink/tps27081a.pdf) from TI,
as the prior wasn't available.
In the datasheet there is something about the slew rate
and selecting the R2 at the source and the C at the output
(depending on capacitive load). Will that be important in my case -
which is basically a moteino mega connected to 4 i2c slaves?
Quote from: designDemon on October 05, 2018, 09:10:41 AM
is this schematic OK?
The schematic is fine, but you might want to increase the value of R25 (10K) to at least 100K or more. That resistor will be conducting most of the time and will affect your battery life.
Quote
I've connected the wakeup pin to the interrupt pin d10
and the done is a GPIO. The jumpers are just in case
I decide I don't wish to power cycle.
(https://ibb.co/guM4ie)
That arrangement should work fine.
Quote
I've replaced the vishay mosfet with tps27081a (http://www.ti.com/lit/ds/symlink/tps27081a.pdf) from TI,
as the prior wasn't available.
The TI part is similar, but I think the Vishay part is a slightly smaller footprint (SC70-6). In any case, the TI part will work fine. You could make a combo SOT23/SC70 footprint on the PCB so you could use either part. Felix did this on his SOT23 breakout board and it works fine.
Quote
In the datasheet there is something about the slew rate
and selecting the R2 at the source and the C at the output
(depending on capacitive load). Will that be important in my case -
which is basically a moteino mega connected to 4 i2c slaves?
If you were switching a high capacitive load then slew rate would be very important. As it is, the slew rate is probably ok since you're effectively clearing the entire device on timeout.
Tom
UPDATED: to correct footprint information.
Thanks for your reply tom.
W.r.t the very valid point that you made here:
Quote from: TomWS on October 05, 2018, 03:19:52 PM
The schematic is fine, but you might want to increase the value of R25 (10K) to at least 100K or more. That resistor will be conducting most of the time and will affect your battery life.That arrangement should work fine.
There is a note in TIs datasheet:
"TI recommends maintaining RR1 > 10 × RR2. The higher value of resistor R1 minimizes
quiescent current when PMOS is on, however, the higher value may adversely impact
OFF-state leakage current. Refer to the load current (ILOAD) specifications in the Electrical
Characteristics table.."
Doesn't this mean that if I use a very high value my off-stage leakage current will be negatively impacted?
Although I don't know how that will actually happen, because the electrical characteristics table that they are referring to has specified leakage currents in the sub uA range for a 10k value I thought 10k should be good enough. What do you say?
Also, I am not specifically driving a capacitive load but is there a threshold value for the effective load capacitance where considering the slew rate becomes important? Then I'll measure the effective load cap and if I am somewhere near the threshold then I'll include provisions for adding the R and C as per the proposed dchematic.
Rgds
Karan
The Off state leakage current will only be a factor if it is so high the drop across R1 doesn't allow turn off. In your case, this would have to be more than 10uA for 100K R1. Further, Off State leakage is not a battery life concern, the switch is only off for 350mS. The ON State current drain of R1 is significant, however as this will be a constant 3.3V / R1.
Re Slew Rate control, it is a good practice to evaluate your capacitive load and adjust accordingly, but you should select values based on desired Slew Rate AND your select R1.
UPDATE: By this I mean, R1 will affect your Turn Off time. Select C value based on the higher R1 value and desired Turn Off time, keeping in mind that the objective is to completely drain your MCU circuit in the alloted 350mS. Once you've chosen C value, THEN you can select an appropriate R2 value to achieve the desired Turn On Slew rate. In this calculation, bear in mind that the effective 'R' value is R1 & R2 in parallel (which I think is already factored into their calculation).
Quote from: TomWS on October 06, 2018, 08:07:06 AM
The Off state leakage current will only be a factor if it is so high the drop across R1 doesn't allow turn off. In your case, this would have to be more than 10uA for 100K R1. Further, Off State leakage is not a battery life concern, the switch is only off for 350mS. The ON State current drain of R1 is significant, however as this will be a constant 3.3V / R1.
Cool. So for the On stage 100k is fine, but for the Off stage can I theoretically compute and confirm that my current will not be more than 10uA?
Quote from: TomWS on October 06, 2018, 08:07:06 AM
Re Slew Rate control, it is a good practice to evaluate your capacitive load and adjust accordingly, but you should select values based on desired Slew Rate AND your select R1.
UPDATE: By this I mean, R1 will affect your Turn Off time. Select C value based on the higher R1 value and desired Turn Off time, keeping in mind that the objective is to completely drain your MCU circuit in the alloted 350mS. Once you've chosen C value, THEN you can select an appropriate R2 value to achieve the desired Turn On Slew rate. In this calculation, bear in mind that the effective 'R' value is R1 & R2 in parallel (which I think is already factored into their calculation).
What should be a safe value for Off-time, t_off? Should it be <=350ms?
I've updated the schematic to include R1 (R25) = 100k , R2 (R26) = ? and C1 (C30) = ?.
If I've understood correctly the mathematically relation is
(R1 || R2) & C1 = k * t _off
In the datasheet there is an equation to compute t_rise (which is the turn on slew rate right?) but
seems to be independent of R2. The only condition for selecting R2 is that it should be <10 * R1.
So can't I simply select R1 = 100k, R2 = 1k and based on safe t_off and t_rise, compute C1?
I think I am confused now.
Quote from: designDemon on October 08, 2018, 10:33:20 AM
Cool. So for the On stage 100k is fine, but for the Off stage can I theoretically compute and confirm that my current will not be more than 10uA?
I'm not sure I understand what you mean here. The leakage current is independent of R1, but the leakage will serve as a bias to the P channel gate based on the leakage current * R1. You need to make sure the drop is well within the turn off voltage of the P FET.
Quote
What should be a safe value for Off-time, t_off? Should it be <=350ms?
I would say you want it well under 350mS because the effect will be a shortening of the power supply off time at the MCU.
Quote
I've updated the schematic to include R1 (R25) = 100k , R2 (R26) = ? and C1 (C30) = ?.
If I've understood correctly the mathematically relation is
(R1 || R2) & C1 = k * t _off
In the datasheet there is an equation to compute t_rise (which is the turn on slew rate right?) but
seems to be independent of R2. The only condition for selecting R2 is that it should be <10 * R1.
The other way around, R1 > 10 * R2 so that the P FET will get a high enough Vgs to turn on, especially if VCC is 3.3V.
Quote
So can't I simply select R1 = 100k, R2 = 1k and based on safe t_off and t_rise, compute C1?
Sure, just bear in mind that the lower R2, the higher the value of C1 and, during turn OFF C1 and R1 form a turn OFF slew rate control.
It's a balancing act and nothing is totally arbitrary.
I'd be inclined to stick with:
1. Pick a reasonable R1. 100K seems reasonable.
2. Pick R2 so that it's about R1 / 10 = 10K, this will give you a Vgs of 3V with 3.3V supply.
3. Calculate C1 based on required turn on Slew Rate with the values above. This SHOULD give you an approximate Slew Rate ratio of 10:1 (turn off vs turn on) due the R1:R2 relationship above.
So I've taken the off time to be max of 35ms.
And by the R1 = 10R2 relation, taken on time (t_rise) to be 3.5ms
and used the equation in the datasheet to calculate C1 (C30 in schematic), keeping R1 and R2 as 100k and 10k respectively.
I am getting a safe range for C1 at .2uF to 1uF. So, ill try accordingly.
I hope this works!
Thanks for showing the way.
Quote from: designDemon on October 10, 2018, 04:44:39 AM
So I've taken the off time to be max of 35ms.
And by the R1 = 10R2 relation, taken on time (t_rise) to be 3.5ms
and used the equation in the datasheet to calculate C2, keeping R1 and R2 as 100k and 10k respectively.
I am getting a safe range for C2 at .2uF to 1uF. So, ill try accordingly.
I hope this works!
Thanks for showing the way.
Just to be clear,
C2 doesn't appear in your posted schematic or in the datasheet. I hope you mean the feedback capacitor between pin 6 (P Channel Gate) and the output pins 2 & 3.
I'm wondering about the VCC discharge time.
You'd need to ensure that when the load switch turns off the switched VCC voltage drops low enough to cleanly power cycle the MCU. That depends on the load the MCU is actually taking at the time. If the MCU is in deep sleep the total current draw on VCC could be a few uA or less, and even a low 1uF bulk capacitor on VCC might take 5 seconds to discharge low enough, which is much longer than the 320ms window.
So it might be a good idea to use the RSTn output to help discharge VCC too as well as turn the load switch off. A schottky diode from the RSTn on the TLP5010 to a 10k pullup on the switched VCC for example.
Mark.
Quote from: perky on October 10, 2018, 07:41:14 PM
I'm wondering about the VCC discharge time.
You'd need to ensure that when the load switch turns off the switched VCC voltage drops low enough to cleanly power cycle the MCU. That depends on the load the MCU is actually taking at the time. If the MCU is in deep sleep the total current draw on VCC could be a few uA or less, and even a low 1uF bulk capacitor on VCC might take 5 seconds to discharge low enough, which is much longer than the 320ms window.
So it might be a good idea to use the RSTn output to help discharge VCC too as well as turn the load switch off. A schottky diode from the RSTn on the TLP5010 to a 10k pullup on the switched VCC for example.
Mark.
Good point Mark and the schottky diode is a good proposal. nRst already has the pull up on its feed to the gate of the N channel FET. A current limiting resistor in series wth the diode should be considered since it's a direct short on the MCU capacitor. Note that the nRst current will be bucking the turn off slew rate of the P Channel FET as well so another reason to consider the current limit.
Quote from: TomWS on October 10, 2018, 08:35:34 PM
A current limiting resistor in series wth the diode should be considered since it's a direct short on the MCU capacitor. Note that the nRst current will be bucking the turn off slew rate of the P Channel FET as well so another reason to consider the current limit.
That's what I meant by 10k pull-up to switched VCC, basically to provide a 10k disharge path to GND during the time RSTn is low.
Quote from: TomWS on October 10, 2018, 07:48:04 AM
Just to be clear, C2 doesn't appear in your posted schematic or in the datasheet. I hope you mean the feedback capacitor between pin 6 (P Channel Gate) and the output pins 2 & 3.
Corrected that. Its
C1 in the datasheet and C30 in my schematic, not C2.
Quote from: perky on October 10, 2018, 07:41:14 PM
A schottky diode from the RSTn on the TLP5010 to a 10k pullup on the switched VCC for example.
Quote from: TomWS on October 10, 2018, 08:35:34 PM
A current limiting resistor in series wth the diode should be considered since it's a direct short on the MCU capacitor. Note that the nRst current will be bucking the turn off slew rate of the P Channel FET as well so another reason to consider the current limit.
Ok. I think i've of board space as this was already cramped in. Could you be kind enough to
please suggest a part no. for this diode, or indicate its critical selection parameters? Also the
values for resistor and where exactly in the current schematic should I place them?
Is it going to be absolutely necessary, or i'll know only after I have the load capacitance?
Quote from: perky on October 11, 2018, 11:15:18 AM
That's what I meant by 10k pull-up to switched VCC, basically to provide a 10k disharge path to GND during the time RSTn is low.
Ah, missed that! So the 10K resistor acts as both the discharge path and the current limit. Very good.
Quote from: designDemon on October 11, 2018, 01:25:43 PM
Could you be kind enough to please suggest a part no. for this diode, or indicate its critical selection parameters? Also the
values for resistor and where exactly in the current schematic should I place them?
Is it going to be absolutely necessary, or i'll know only after I have the load capacitance?
I think you will need it, remember the Moteino (and the RFM69) has bulk capacitance too. I personally would use a BAT54 (SOT23 package). Connect as:
10k BAT54
3.3V----/\/\/\/\/------|>|------ON/OFF
A K
So when ON/OFF goes low (which is connected to RSTn of the TPL5010), the load switch will turn off and the 10k will discharge the 3.3V. When it's turned back on the diode will isolate ON/OFF and 3.3V will then come back up, hopefully power-resetting the MCU.
Edit: The diode might not be needed actually. After all when ON/OFF is low the load switch is off, and when high it is on. Connecting the resistor directly to ON/OFF might be all that's needed. There would be a potential divider on the ON/OFF signal though, so the diode approach is cleaner.
I had one concern with this.
When the reset pin goes low, because the fet's switching off
time is slew rate controlled, will this not create a discharge path
for the 3.3V to Ground even before the switch is turned off?
Is that not going to be a concern?
Also, note that the ON/OFF pin is already pulled up to the
the Vin to the fet and watchdog. And Vcc and Vin already
have the slew rate R1-C1 pair between them in series.
So as soon as the ON/Off pin is toggled low the
circuit becomes (check schematic)
_____________________--||--___________________________________
| 0.2uF |
| |
(
[email protected])_____/\/\10K/\/\____
(On/OFF @ 0V)_________/\/\10k/\/\___(
[email protected])
So while the intention is to discharge Vcc, the .2uF cap will end up getting charged at
the same time. How will all this work out in the end?
Quote from: perky on October 11, 2018, 06:11:26 PM
personally would use a BAT54 (SOT23 package).
I need something smaller. Can I use this one: BAT5402VH6327XTSA1 (https://www.infineon.com/dgdl/Infineon-BAT54SERIES-DS-v01_01-en.pdf?fileId=db3a304314dca3890115190b74210ea6)
Quote from: designDemon on October 12, 2018, 10:59:48 AM
When the reset pin goes low, because the fet's switching off
time is slew rate controlled, will this not create a discharge path
for the 3.3V to Ground even before the switch is turned off?
This shouldn't be a problem. It's the rate of change of
voltage on the switched output that's fed back via a capacitor to the gate of the top P-FET, so the current that is being supplied by the switched output doesn't have much effect.
Quote from: designDemon on October 12, 2018, 10:59:48 AM
Also, note that the ON/OFF pin is already pulled up to the
the Vin to the fet and watchdog. And Vcc and Vin already
have the slew rate R1-C1 pair between them in series.
So as soon as the ON/Off pin is toggled low the
circuit becomes (check schematic)
_____________________--||--___________________________________
| 0.2uF |
| |
([email protected])_____/\/\10K/\/\____(On/OFF @ 0V)_________/\/\10k/\/\___([email protected])
So while the intention is to discharge Vcc, the .2uF cap will end up getting charged at
the same time. How will all this work out in the end?
This diagram appears to be wrong. The ON/OFF pullup to Vin is 10k, the resistor that is in series with C1 is a different resistor, 100k. I think you've confused the ON/OFF pullup with that resistor. But that 100k/C1 junction is itself connected to the gate of the top P-FET, and the rate of change of
voltage will control how much that P-FET is turned on so as to maintain that rate of change. It is essentially independent of the current being sourced on the Vcc output. So the additional current taken by the Vcc 10k resistor while discharging won't affect the rise or fall time of Vcc, because of the voltage feedback.
Quote from: designDemon on October 12, 2018, 10:59:48 AM
I need something smaller. Can I use this one: BAT5402VH6327XTSA1 (https://www.infineon.com/dgdl/Infineon-BAT54SERIES-DS-v01_01-en.pdf?fileId=db3a304314dca3890115190b74210ea6)
Yes that's fine, it's just a generic BAT54 in a SC79 package.
Mark.