Using TPL5110 as Watchdog

[designDemon]

The Off state leakage current will only be a factor if it is so high the drop across R1 doesn't allow turn off.  In your case, this would have to be more than 10uA for 100K R1.   Further, Off State leakage is not a battery life concern, the switch is only off for 350mS.  The ON State current drain of R1 is significant, however as this will be a constant 3.3V / R1.

Cool. So for the On stage 100k is fine, but for the Off stage can I theoretically compute and confirm that my current will not be more than 10uA?

Re Slew Rate control, it is a good practice to evaluate your capacitive load and adjust accordingly, but you should select values based on desired Slew Rate AND your select R1.
UPDATE: By this I mean, R1 will affect your Turn Off time.  Select C value based on the higher R1 value and desired Turn Off time, keeping in mind that the objective is to completely drain your MCU circuit in the alloted 350mS.  Once you've chosen C value, THEN you can select an appropriate R2 value to achieve the desired Turn On Slew rate.  In this calculation, bear in mind that the effective 'R' value is R1 & R2 in parallel (which I think is already factored into their calculation).

What should be a safe value for Off-time, t_off? Should it be <=350ms?
I've updated the schematic to include R1 (R25) = 100k , R2 (R26) = ? and C1 (C30) = ?.
If I've understood correctly the mathematically relation is
(R1 || R2) & C1 = k * t _off

In the datasheet there is an equation to compute t_rise (which is the turn on slew rate right?) but
seems to be independent of R2. The only condition for selecting R2 is that it should be <10 * R1.

So can't I simply select R1 = 100k, R2 = 1k and based on safe t_off and t_rise, compute C1?

I think I am confused now.

[TomWS]

Cool. So for the On stage 100k is fine, but for the Off stage can I theoretically compute and confirm that my current will not be more than 10uA?

I'm not sure I understand what you mean here.  The leakage current is independent of R1, but the leakage will serve as a bias to the P channel gate based on the leakage current * R1.  You need to make sure the drop is well within the turn off voltage of the P FET.

What should be a safe value for Off-time, t_off? Should it be <=350ms?

I would say you want it well under 350mS because the effect will be a shortening of the power supply off time at the MCU.

I've updated the schematic to include R1 (R25) = 100k , R2 (R26) = ? and C1 (C30) = ?.
If I've understood correctly the mathematically relation is
(R1 || R2) & C1 = k * t _off

In the datasheet there is an equation to compute t_rise (which is the turn on slew rate right?) but
seems to be independent of R2. The only condition for selecting R2 is that it should be <10 * R1.

The other way around, R1 > 10 * R2 so that the P FET will get a high enough Vgs to turn on, especially if VCC is 3.3V.

So can't I simply select R1 = 100k, R2 = 1k and based on safe t_off and t_rise, compute C1?

Sure, just bear in mind that the lower R2, the higher the value of C1 and, during turn OFF C1 and R1 form a turn OFF slew rate control.

It's a balancing act and nothing is totally arbitrary.

I'd be inclined to stick with:
1. Pick a reasonable R1.  100K seems reasonable.
2. Pick R2 so that it's about R1 / 10 = 10K, this will give you a Vgs of 3V with 3.3V supply.
3. Calculate C1 based on required turn on Slew Rate with the values above.  This SHOULD give you an approximate Slew Rate ratio of 10:1 (turn off vs turn on) due the R1:R2 relationship above.

[designDemon]

So I've taken the off time to be max of 35ms.
And by the R1 = 10R2 relation, taken on time (t_rise) to be 3.5ms
and used the equation in the datasheet to calculate C1 (C30 in schematic), keeping R1 and R2 as 100k and 10k respectively.

I am getting a safe range for C1 at .2uF to 1uF. So, ill try accordingly.
I hope this works!

Thanks for showing the way.

[TomWS]

So I've taken the off time to be max of 35ms.
And by the R1 = 10R2 relation, taken on time (t_rise) to be 3.5ms
and used the equation in the datasheet to calculate C2, keeping R1 and R2 as 100k and 10k respectively.

I am getting a safe range for C2 at .2uF to 1uF. So, ill try accordingly.
I hope this works!

Thanks for showing the way.

Just to be clear, C2 doesn't appear in your posted schematic or in the datasheet.  I hope you mean the feedback capacitor between pin 6 (P Channel Gate) and the output pins 2 & 3.

[perky]

I'm wondering about the VCC discharge time.

You'd need to ensure that when the load switch turns off the switched VCC voltage drops low enough to cleanly power cycle the MCU. That depends on the load the MCU is actually taking at the time. If the MCU is in deep sleep the total current draw on VCC could be a few uA or less, and even a low 1uF bulk capacitor on VCC might take 5 seconds to discharge low enough, which is much longer than the 320ms window.

So it might be a good idea to use the RSTn output to help discharge VCC too as well as turn the load switch off. A schottky diode from the RSTn on the TLP5010 to a 10k pullup on the switched VCC for example.

Mark.

[TomWS]

I'm wondering about the VCC discharge time.

You'd need to ensure that when the load switch turns off the switched VCC voltage drops low enough to cleanly power cycle the MCU. That depends on the load the MCU is actually taking at the time. If the MCU is in deep sleep the total current draw on VCC could be a few uA or less, and even a low 1uF bulk capacitor on VCC might take 5 seconds to discharge low enough, which is much longer than the 320ms window.

So it might be a good idea to use the RSTn output to help discharge VCC too as well as turn the load switch off. A schottky diode from the RSTn on the TLP5010 to a 10k pullup on the switched VCC for example.

Mark.

Good point Mark and the schottky diode is a good proposal. nRst already has the pull up on its feed to the gate of the N channel FET.  A current limiting resistor in series wth the diode should be considered since it's a direct short on the MCU capacitor.  Note that the nRst current will be bucking the turn off slew rate of the P Channel FET as well so another reason to consider the current limit.

[perky]

A current limiting resistor in series wth the diode should be considered since it's a direct short on the MCU capacitor.  Note that the nRst current will be bucking the turn off slew rate of the P Channel FET as well so another reason to consider the current limit.

That's what I meant by 10k pull-up to switched VCC, basically to provide a 10k disharge path to GND during the time RSTn is low.

[designDemon]

Just to be clear, C2 doesn't appear in your posted schematic or in the datasheet.  I hope you mean the feedback capacitor between pin 6 (P Channel Gate) and the output pins 2 & 3.

Corrected that. Its C1 in the datasheet and C30 in my schematic, not C2.

A schottky diode from the RSTn on the TLP5010 to a 10k pullup on the switched VCC for example.

A current limiting resistor in series wth the diode should be considered since it's a direct short on the MCU capacitor.  Note that the nRst current will be bucking the turn off slew rate of the P Channel FET as well so another reason to consider the current limit.

Ok. I think i've of board space as this was already cramped in. Could you be kind enough to
please suggest a part no. for this diode, or indicate its critical selection parameters? Also the
values for resistor and where exactly in the current schematic should I place them?
Is it going to be absolutely necessary, or i'll know only after I have the load capacitance?

[TomWS]

That's what I meant by 10k pull-up to switched VCC, basically to provide a 10k disharge path to GND during the time RSTn is low.

Ah, missed that!  So the 10K resistor acts as both the discharge path and the current limit.  Very good.

[perky]

Could you be kind enough to please suggest a part no. for this diode, or indicate its critical selection parameters? Also the
values for resistor and where exactly in the current schematic should I place them?
Is it going to be absolutely necessary, or i'll know only after I have the load capacitance?

I think you will need it, remember the Moteino (and the RFM69) has bulk capacitance too. I personally would use a BAT54 (SOT23 package). Connect as:

                10k        BAT54
3.3V----/\/\/\/\/------|>|------ON/OFF
                              A    K

So when ON/OFF goes low (which is connected to RSTn of the TPL5010), the load switch will turn off and the 10k will discharge the 3.3V. When it's turned back on the diode will isolate ON/OFF and 3.3V will then come back up, hopefully power-resetting the MCU.

Edit: The diode might not be needed actually. After all when ON/OFF is low the load switch is off, and when high it is on. Connecting the resistor directly to ON/OFF might be all that's needed. There would be a potential divider on the ON/OFF signal though, so the diode approach is cleaner.

[designDemon]

I had one concern with this.

When the reset pin goes low, because the fet's switching off
time is slew rate controlled, will this not create a discharge path
for the 3.3V to Ground even before the switch is turned off?

Is that not going to be a concern?

Also, note that the ON/OFF pin is already pulled up to the
the Vin to the fet and watchdog. And Vcc and Vin already
have the slew rate R1-C1 pair between them in series.
So as soon as the ON/Off pin is toggled low the
circuit becomes (check schematic)


     _____________________--||--___________________________________
    |                                     0.2uF                                                               |
    |                                                                                                            |
([email protected])_____/\/\10K/\/\____(On/OFF @ 0V)_________/\/\10k/\/\___([email protected])


So while the intention is to discharge Vcc, the .2uF cap will end up getting charged at
the same time. How will all this work out in the end?

personally would use a BAT54 (SOT23 package).

I need something smaller. Can I use this one: BAT5402VH6327XTSA1

[perky]

When the reset pin goes low, because the fet's switching off
time is slew rate controlled, will this not create a discharge path
for the 3.3V to Ground even before the switch is turned off?

This shouldn't be a problem. It's the rate of change of voltage on the switched output that's fed back via a capacitor to the gate of the top P-FET, so the current that is being supplied by the switched output doesn't have much effect.

Also, note that the ON/OFF pin is already pulled up to the
the Vin to the fet and watchdog. And Vcc and Vin already
have the slew rate R1-C1 pair between them in series.
So as soon as the ON/Off pin is toggled low the
circuit becomes (check schematic)

     _____________________--||--___________________________________
    |                                     0.2uF                                                               |
    |                                                                                                            |
([email protected])_____/\/\10K/\/\____(On/OFF @ 0V)_________/\/\10k/\/\___([email protected])

So while the intention is to discharge Vcc, the .2uF cap will end up getting charged at
the same time. How will all this work out in the end?

This diagram appears to be wrong. The ON/OFF pullup to Vin is 10k, the resistor that is in series with C1 is a different resistor, 100k. I think you've confused the ON/OFF pullup with that resistor. But that 100k/C1 junction is itself connected to the gate of the top P-FET, and the rate of change of voltage will control how much that P-FET is turned on so as to maintain that rate of change. It is essentially independent of the current being sourced on the Vcc output. So the additional current taken by the Vcc 10k resistor while discharging won't affect the rise or fall time of Vcc, because of the voltage feedback.

I need something smaller. Can I use this one: BAT5402VH6327XTSA1

Yes that's fine, it's just a generic BAT54 in a SC79 package.

Mark.