Recommended through hole N mosfets?

Started by gregcope, May 09, 2016, 01:55:46 PM

TomWS

#15
Here is a good intro article about LEDs: http://www.theledlight.com/LED101.html

Electrically, an LED looks like a 'soft', high voltage drop, silicon diode, it will not conduct (much) until there is sufficient voltage to forward bias the diode.  Then, as current builds up, the voltage will increase with increased current.  A green LED, will begin to conduct around 2volts, so, if you want a 6 volt protection, you'll need at least 3 Green LEDs in series.  Note that each color/efficiency rated LED has its own voltage drop so 2V would be unique to Green, 'normal' efficiency.

Now, as to 'seeing' the LEDs light, your difficulty is the wide range of voltage that you need to deal with.  At 11V VCC you'll have 5 volts across the resistor (assuming 3 Green LEDs).  At 32 volts you'll have about 20 volts across the resistor (due to 2.5V drop at each LED due to increased current), which will give you a 4 to one range of current.  Max operating current on the LED will probably be around 25mA so your resistor will be R=V/I or 20/0.025 = 800 ohms (820ohms is close enough) and should be a 1W resistor to handle worst case power.   This resistor will give you approximately 6mA at your LEDs with 11V VCC.  This should be enough to light them, but is obviously 4 times dimmer than max brightness (your eye won't notice this much brightness change, however).

Finally, note, to 'see' that the charger is on, you are throwing away 25mA in the worst case.

A 10V zener diode (1N5240B), on the other hand, would provide 8V with only 3uA of bias, allowing you to substantially decrease the power wasted by the circuit.  If you put one of these (cathode to VCC, anode to Gate) on your transistor, supply 10uA at 1V drop resistor (100K ohm) with a capacitor matching the DrainGate parasitic capacitance of the power transistor in parallel with the 100K resistor, you won't draw more than 220uA in the worst case condition.  You should add a 1M ohm resistor Source-Gate on the power transistor to ensure that it is off when the N Channel FET is off.

Tom
Update: changed diode analogy and a few cleanup touches.

gregcope

I think I am nearly there.

I am missing a resistor.  Not sure where the 100K goes?

See attachement for a really rough sketch of a circuit

gregcope

Re-reading for the nth time, I think I am missing a capacitor in parallel with the 100K too.

TomWS

Quote from: gregcope on July 11, 2016, 04:52:38 PM
I think I am nearly there.

I am missing a resistor.  Not sure where the 100K goes?

See attachement for a really rough sketch of a circuit
Not bad, Greg, not bad.  The 100K resistor goes between the Drain of the N Channel FET and the Gate of the P Channel power FET.  A small cap across this resistor will improve the switching speed but probably isn't essential given your light load.  The cap should match the parasitic capacitance of the P Channel FET.  I'd have to take a look at the datasheet to see if they spec this.  As a really rough SWAG, I'd use between 100pf-470pf.

Tom


gregcope

Many thanks Tom!

V1.1 including 100K.

Also the Data sheet has this, which I think it what you are refering to (Capacitance wise);


TomWS

Quote from: gregcope on July 12, 2016, 02:20:14 AM
Many thanks Tom!

V1.1 including 100K.

Also the Data sheet has this, which I think it what you are refering to (Capacitance wise);
I don't see the capacitor in V1.1.  Yes, Figure 5 is the correct data and you want to use Cgd (Crss in the chart).  I'd use 100pF from this data and it should be put in parallel to R4 (100K).

Maybe you'll get your monitor operating this season!  Happy boating!

Tom

perky

#21
There is an argument that speeding up the switching is actually what you don't want with load switches, and instead it should switch in its linear region using slew rate control. Otherwise you're going to get large current spikes as the switched in caps are charged up. Also there's a linear regulator rather than a buck regulator and I don't know what the power dissipation of that could be as it could be dropping a lot of volts. If it's charging a LiPo I presume the current is not negligable.

Mark.

TomWS

Quote from: perky on July 12, 2016, 07:59:15 AM
There is an argument that speeding up the switching is actually what you don't want with load switches, and instead it should switch in its linear region using slew rate control. Otherwise you're going to get large current spikes as the switched in caps are charged up. Also there's a linear regulator rather than a buck regulator and I don't know what the power dissipation of that could be as it could be dropping a lot of volts. If it's charging a LiPo I presume the current is not negligable.

Mark.
Valid points, Mark.  In this case, since we have so little data on what is actually being switched, I erred on the side of keeping the P FET in SOA rather than worrying about surge on a rather hefty supply (bank of SLAs).   Also, its easier to snip a capacitor than add one later on (after the P FET is toasted  ;)

Tom

gregcope

Will add a capcitor on v1.2 when I get home later!

gregcope

Also the 7-36v regulator that is being switched is the OKI one that Felix recommends;

http://power.murata.com/data/power/oki-78sr.pdf

perky

Quote from: gregcope on July 12, 2016, 12:59:24 PM
Also the 7-36v regulator that is being switched is the OKI one that Felix recommends;

http://power.murata.com/data/power/oki-78sr.pdf

OK, a switching regulator. This will have a capacitor on board and one on board on its output. Personally I would use a slew rate controlled load switch circuit for this just to keep the spikes down on turn on in case it is a problem, but YMMV.

Mark.

gregcope

Added 100pF to as C2.  Version 1.2