I think there are equations in the sx1231h datasheet that allows you to calculate the minimum time needed to ensure the bit synchronizer locks, and there's a dependence on bit rate and RxBw (TS_RE), plus 12 bits of received preamble.

Back of a fag packet calculation, For RxBw = 500kHz, Tbit = 1/300kHz with no AGC or AFC:

TS_RE = Tana + Tcf + Tdcc + Trssi + Trssi

Where:

Tana = 20us

Tcf = 21/(4*RxBw) = 10.5us

Tdcc = max(8 , 2^(round(log2(8.RxBw.Tbit)+1)) / (4.RxBw) = 16 / (4*RxBw) = 8us

Trrsi = 2 * Tbit = 6.7us

So TS_RE = 20us + 10.5us + 8us + 6.7us + 6.7us = 52us, or 15.6 Tbits.

Then you need to add 12 bits for the bit synchronizer to lock, so you'll need 27.6 Tbits, or

*4 bytes of preamble* Mark.