1. It is a sanity test that the SPI bus is actually talking to a live RF module - you can see that this code is very early in the init sequence - the test patterns (alternating one/zero) are of course not relevant to later when the module is fully initialised and active.
2. Synch pattern length is more about immunity to noise - the longer the length the less chance that random input bit streams will trigger a false packet decode
3. Yes