accurate Moteino battery voltage monitoring

[emjay]

@ChemE,

Ok, then if you have a look at the Moteino schematic you will see a cap hung off Aref for noise reduction.
Perky is correct - when switching on the internal reference, it can only rise as fast as that cap allows.
You can reduce the cap value (and hence the lag) somewhat without noise on Vref becoming too much of a problem.

[ChemE]

Ah interesting.  Another instance where a chemical engineering education is unhelpful   So a smaller cap *might* be a means of further reducing the power consumption in that a battery voltage could be read faster provided it wasn't so much smaller as to make the line noisy.  Interesting, thanks gents.

[perky]

There's also the bandgap startup time to consider (40us typical, 70us max), that'll combine with the RC constant and could explain your 100us settling time.
Mark.

[perky]

This Aref settling time may well have implications for low power. Those wishing to do fast ADC reads on wakeup and then go back to sleep straight away may have to do a 2 stage wakeup and use a timer to time the 100us settling time:

1) Wake up from deep sleep
2) Start bandgap and mux onto Aref
3) Start timer to interrupt after 100us
4) Go to sleep with only timer clock running
5) Wake up from timer interrupt and read ADC
6) Go back to deep sleep

Mark.

[ChemE]

I follow you.  This strategy vs. cooling my heels for 100us may well be testable via my ultracapacitor.  Given that sensing battery voltage is a pretty fundamental part of most battery powered nodes, I plan to do some further investigating to see if some extra coulombs can be squeezed out.