Author Topic: A new sleep mode using 225 nA  (Read 11510 times)

WhiteHare

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Re: A new sleep mode using 225 nA
« Reply #15 on: February 09, 2016, 03:00:23 PM »
Thanks for the suggestion!  Of potential interest, I notice that jcw (the jeelabs guy), who has a related objective and constraints with his RFM69 + mcu project, started with 100uF caps for energy storage but later decided to upgrade to 470uF:  http://jeelabs.org/2015/05/13/micro-power-snitch-success/index.html
« Last Edit: February 09, 2016, 03:16:18 PM by WhiteHare »

joelucid

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Re: A new sleep mode using 225 nA
« Reply #16 on: February 10, 2016, 08:33:11 AM »
Quote
started with 100uF caps for energy storage but later decided to upgrade to 470uF

That obviously depends on what the cap will be driving. His project is also different in that leakage doesn't matter. 470uF electrolytic caps are not low leakage.

WhiteHare

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Re: A new sleep mode using 225 nA
« Reply #17 on: February 11, 2016, 01:27:36 PM »
The way to achieve voltage conversion with very high efficiency at ultra low currents is to only run the converter intermittently and smartly disconnect it in between.

I took another pass at this, and it looks as though the savings would accrue from avoiding the quiescent current, which on an LTC3531-3.3 would be 7uA.  Looks as though the WAKE pin on a TPL5010 could simply be wired to the !STDN pin on a LTC3531-3.3 (http://cds.linear.com/docs/en/datasheet/3531fb.pdf), used to charge the cap, and voilą.  The WAKE pulse lasts 20ms, and the turn-on time for the LTC3531-3.3 takes less than 2ms, so it can buck/boost a solid 18ms per cycle with no need to wake the atmega.  So, doing the tally for the "typical" case between wake-ups:
sleeping atmega: 100nA
sleeping RFM69: 100nA
shutdown LTC3531-3.3: 100nA
TPL5010:  35nA
Total: 335nA
So, not as thrifty as your circuit between wake events.  I don't know what the periodicity of the wake-cycle would be, but if I were to go this route, I'd probably use either an RTC or another TPL5010 to wake the atmega as infrequently as possible.  So, that would bring the total to, say, 370nA. 

If those numbers proved out, that would open whole new horizons.     What's next after that?   ;)


TomWS

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Re: A new sleep mode using 225 nA
« Reply #18 on: February 11, 2016, 02:01:53 PM »
Looks as though the WAKE pin on a TPL5010 could simply be wired to the !STDN pin on a LTC3531-3.3 (http://cds.linear.com/docs/en/datasheet/3531fb.pdf), used to charge the cap, and voilą.  The WAKE pulse lasts 20ms, and the turn-on time for the LTC3531-3.3 takes less than 2ms, so it can buck/boost a solid 18ms per cycle with no need to wake the atmega.
The TPL5010 doesn't produce a WAKE pulse without receiving a DONE pulse from the MCU - that's the watchdog interlock.  It will produce a periodic RESET, but that's 320mS long.

Tom

joelucid

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Re: A new sleep mode using 225 nA
« Reply #19 on: February 11, 2016, 02:03:37 PM »
Quote
shutdown LTC3531-3.3: 100nA

Except you'll find that shutdown will drain the cap - so you need to do a bit more. And if wake is on shutdown how does the system initially bootstrap? On the upside once this works you can put a factor of 1/3rd to your currents when using a 9V battery.

But what I meant with the tpl5010 being the simplest route to very low power is that you could just add it to an existing Moteino and have it provide the wakes. Drop the LDO, run from 2x aaa or coin and expend 280nA. Only takes one chip and doesn't require hugely restructuring your app. It's really simple.

WhiteHare

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Re: A new sleep mode using 225 nA
« Reply #20 on: February 11, 2016, 05:19:34 PM »

But what I meant with the tpl5010 being the simplest route to very low power is that you could just add it to an existing Moteino and have it provide the wakes. Drop the LDO, run from 2x aaa or coin and expend 280nA. Only takes one chip and doesn't require hugely restructuring your app. It's really simple.

Given the complexity of some of the alternatives, simple sounds pretty good.  :)

Is 280nA the number you calculated as the average current spread over a 2 hour cycle (the max period for a tpl5010), including the current from the brief atmega wakeup?  If that's what your math shows, then that does sound hard to beat.

As for a voltage boost scenario, the benefits of avoiding the quiescent current seem like they would be big enough that I wonder if specialized boost chips already exist that incorporate a similar circuit?

[Edit: wait, I just did the math.  If all the atmega does is wakeup once every 2 hours for 3ms (including the wake-up time) at an average current of 2ma during that 3ms, then the that increases the average current drain by just 1 nanoamp over that two hour period.  In that case, the average current drain would be something like 236na (= 100na atmega + 100na RFM69 + 35na tpl5010 + 1na wake-up overhead) amortized over the two hours.]
« Last Edit: February 11, 2016, 06:07:01 PM by WhiteHare »

joelucid

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Re: A new sleep mode using 225 nA
« Reply #21 on: February 11, 2016, 05:57:16 PM »
I'm just counting 100nA for the radio, 150nA for the 328p and 30nA for the 5010. Brief awakenings cost next to nothing. Of course measurements and updates are extra.

That works if you don't need a voltage converter. And it's hard to beat unless you use the am1805.

Of course just to play Devils advocate: for my latest th mote I decided to go plain 328p + rfm69 with a new power optimization of listen mode and I'll come out at maybe 1.8uA. Sounds huge - but it still gives you close to a decade on cr2032 and it is less to solder. Which you will appreciate if you ever pass into the zone of custom pcb creation ...

WhiteHare

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Re: A new sleep mode using 225 nA
« Reply #22 on: February 11, 2016, 06:12:57 PM »
Oops, that's right: 150na for the atmega, not 100na.  So, revising my math, that means 286na average current drain, which is in close agreement with your math.   Cool!  :)

[Edit: Even if it were to wake up every minute, then (if the wake-up current assumptions are reasonable), it would increase the average current by just 100na.  i.e. 385na average.  If it were to wake-up every 4 seconds, then the average current drain would be roughly equal to what you calculated above for listen-mode.

So, if one minute granularity were "good enough," I suppose you could afford to request the precise time every so often so as to keep things on track for a scheduled event, like maybe turning on/off some lights at a particular time. For finer granularity, you could switch-over to a more regular low power sleep library when you're within a minute of the event.  If using the RTC without a crystal oscillator, I suppose a similar strategy would also work to compensate for the lower ppm clock accuracy.]
« Last Edit: February 11, 2016, 07:26:49 PM by WhiteHare »

WhiteHare

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Re: A new sleep mode using 225 nA
« Reply #23 on: October 25, 2016, 04:10:22 PM »
I made a breakout board for the Si1869DH, and I can post the gerber and drilling files which are conveniently zipped and ready for fab if anyone would like it.  It would, for example, cost $0.20/board on OSH Park, including shipping (minimum order 3).

The datasheet (http://www.vishay.com/docs/73449/si1869dh.pdf) doesn't include a land pattern, so I used the land pattern for the SC70 on page 44 of http://ww1.microchip.com/downloads/en/PackagingSpec/00049BK.pdf

If there's interest, I can make one for the Si2356DS also (see original post), and then folks can play around with the OP circuit on a breadboard.
« Last Edit: October 25, 2016, 04:54:01 PM by WhiteHare »

perky

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Re: A new sleep mode using 225 nA
« Reply #24 on: October 25, 2016, 05:25:22 PM »
I'm afraid the leakage current of the FETs might scupper this idea. The  SI2356DS for example has 1uA max zero gate voltage drain current (Idss) at 25 deg C (admittedly at 40V), and this rises to 10uA at 40V for 55 deg C. It'll be less for lower voltages of course but it's still significant, and your 60M pull-up might not actually pull it up leaving the load switch FET permanently on. You are going to have to find ultra low leakage FETs I think.
Mark.
« Last Edit: October 25, 2016, 05:27:01 PM by perky »

WhiteHare

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Re: A new sleep mode using 225 nA
« Reply #25 on: October 25, 2016, 06:41:32 PM »
I'm afraid the leakage current of the FETs might scupper this idea. The  SI2356DS for example has 1uA max zero gate voltage drain current (Idss) at 25 deg C (admittedly at 40V), and this rises to 10uA at 40V for 55 deg C. It'll be less for lower voltages of course but it's still significant, and your 60M pull-up might not actually pull it up leaving the load switch FET permanently on. You are going to have to find ultra low leakage FETs I think.
Mark.

@perky
Would REG02 serve the intended purpose of the OP circuit?  I made a breakout for it too that I'd be happy to share if anyone wants it.

perky

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Re: A new sleep mode using 225 nA
« Reply #26 on: October 25, 2016, 07:26:13 PM »
What is a REG02?

WhiteHare

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Re: A new sleep mode using 225 nA
« Reply #27 on: October 25, 2016, 07:41:26 PM »
What is a REG02?

Sorry, I should have said REG102:  http://www.ti.com/lit/ds/symlink/reg102.pdf

The idea being to charge up the capacitor using the REG102 and then the atmega328p DISABLEs it, similar (if I'm understanding the notion) as to what the OP circuit was doing.  However, the quiescent current of the REG102 in the OFF state (i.e. when DISABLed) is much lower--just 10na.  When the voltage on the capacitor drops low enough, the atmega328p ENABLEs the REG102 again, and the cycle repeats.

perky

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Re: A new sleep mode using 225 nA
« Reply #28 on: October 25, 2016, 08:31:06 PM »
That's very interesting. This regulator specifies the output impedance as 600mR when VIN is less than the regulation voltage, which LDOs usually do but not generally specified explictly (it's actually related to the droput voltage and current). There's the ground current and also the enable current which are very low, they're logarithmic with temperature but if its below 50 deg C they're still pretty low. If you can cope with the 600mR output impedance this stands a much better chance of working I think.
Mark.

joelucid

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Re: A new sleep mode using 225 nA
« Reply #29 on: October 26, 2016, 08:46:49 AM »
FWIW these fets worked fine when I tested this setup. Generally I've found that the typical values of the various leakage currents are often an order of magnitude less than what's spec'd as max.